Ternary code error detector for a time-division multiplex, pulse-code modulation system

ABSTRACT

In a time-division multiplex, pulse-code modulation system, each sequence of four binary pulses representing information is converted to a group of three ternary pulses for transmission to a receiver. The conversions are made either in a positive mode if the prior net polarity is negative or in a negative mode if the prior net polarity is zero or positive. Use of the positive and negative modes insures that the net positive and the net negative polarities are kept within selected limits. At the receiver, a ternary code error detector is provided to detect if the net positive polarity or if the net negative polarity exceed the selected limits. If either selected limit is exceeded, the error detector produces an error signal which can be used in any way desired, such as to switch to other multiplexing equipment, or to switch to other transmission lines, or to produce any sort of desired alarm.

United States Patent Smith, Jr. et al.

[ 1 TERNARY CODE ERROR DETECTOR FOR A TIME-DIVISION MULTIPLEX, PULSE-CODE MODULATION SYSTEM Inventors: James S. Smith, Jr.; James W.

Williams, both of Lynchburg, Va.

Assignee: General Electric Company, Lynchburg, Va.

Filed: Sept. 10, 1973 Appl. No.: 395,833

[56] References Cited UNITED STATES PATENTS 4/1971 Gunn 340/1461 AB 11/1971 Tang et a1. 340/1461 AB 7/1973 Gibson 340/1461 R 9/1973 Gibson 340/1461 AB OTHER PUBLICATIONS Croisier, A. Introduction to Pseudotemary Transmis- Oct. 15, 1974 sion Codes," in IBM J. Res. Develop, July 1970, p. 361 TK7885.A1.

Primary Examiner-Malcolm A. Morrison Assistant Examiner-R. Stephen Dildine, Jr.

[ 5 7 ABSTRACT In a time-division multiplex, pulse-code modulation system, each sequence of four binary pulses representing information is converted to a group of three ternary pulses for transmission to a receiver. The conversions are made either in a positive mode if the prior net polarity is negative or in a negative mode if the prior net polarity is zeroor positive. Use of the positive and negative modes insures that the net positive and the net negative polarities are kept within selected limits. At the receiver, a ternary code error detector is provided to detect if the net positive polarity or if the net negative polarity exceed the selected limits. If either selected limit is exceeded, the error detector produces an error signal which can be used in any way desired, such as to switch to other multiplexing equipment, or to switch to other transmission lines, or to produce any sort of desired alarm.

3 Claims, 5 Drawing Figures TERNARY PULSES PW FROM LINE l l 2 4 +lNPUT UP-DOWN 1 COUNTER l 2 4 INPUT ERROR SIGNAL PAIENIEIJ I 3842,40 1

SHEET 30F 4 FIG?) BINARY-TERNARY (4'3) CONVERSION CODE BINARY TERNARY GROUP POLARITY GROUP osmvs MODE NEGATIVE MODE WEIGHT 0000 o 0 o 0 OOOI 0 0 o 0 0010 o o o 001 0 0 0 7 0 I00 0 0 o 0| 0 0 0 I000 0 0 o o now low o o 2 10: I 0 o 2 I I00 o o o I I I0 I POSITIVE MODE IS USED IF PRIOR N'ET POLARITY WEIGHT IS NEGATIVE NEGATIVE MODE IS USED IF PRIOR NET POLARITY WEIGHT IS ZERO OR POSITIVE TERNARY PULSES PW FROM LINE PATENIEUUU 1 51924 FIG.4

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CLOSED CLOSED CLOSED OPEN OPEN* CLOSED CLOSED CLOSED CLOSED CLOSED CLOSEID CLOSED CLOSED CLOSED CLOSED CLOSED CLOSED OLOsEO CLOSE-D Ol-N CLOSED CLOSED CLOSED CLOSED CLOSED CLOSED CLOSED CLOSED CLOSED CLOSED CLOSED CLOSED CLOSED OPEN OPEN" CLOSED I CLOSED CLOSED CLOSED SIGNAL TERNARY CODE ERROR DETECTOR FOR A TIME-DIVISION MULTIPLEX, PULSE-CODE MODULATION SYSTEM CROSS-REFERENCE TO RELATED APPLICATIONS This application describes an invention which is particularly useful in a time-division multiplex, pulse-code modulation system as described in a patent application entitled Improved Communication System Using Time-Division Multiplexing and Pulse-Code Modulationfiled Feb. I, 1971, Ser. No. 111,436, and assigned to the General Electric Company.

BACKGROUND OF THE INVENTION Our invention relates to a ternary code error detector for a time-division multiplex, pulse-code modulation system, and particularly to such an error detector for detecting if the net positive polarity or if net negative polarity of the ternary code exceed selected limits.

Communication systems using time-division multiplexing and pulse-code modulation are used to provide a plurality of relatively low noise, easily regenerated communication channels over a single communication circuit. Such systems are described in considerable detail in a book entitled Transmission Systems for Communications, by Members of the Technical Staff, Bell Telephone Laboratories, Fourth Edition, 1970. One such system, designated T1 by the Bell Telephone System, is used extensively for transmission. The T1 system provides 24 channels over two pairs of wires, one pair of wires being used for each direction of transmission. In order that more telephone circuits can be provided over the same wire pairs, a new time-division multiplex, pulse-code modulation system has been devised. This new system is designated the TCS-27A or the TCS-28 pulse-code modulation carrier system, and is generally described in the patent application referred to above. This system uses time-division multiplexing and pulse-code modulation of 36 channels for voice, and a separate 37th channel for signaling, alarms, and framing. Each of the 36 voice channels is amplitude sampled 8,000 times per second, and the samples are time-division multiplexed. The amplitude of each of the multiplexed samples is then encoded by seven binary pulses. Five binary pulses representing signaling, alarms, and framing are multiplexed after each 252 pulses (36 voice channels each having seven pulses per channel) to complete one frame comprising 257 pulses. Twelve such frames comprise a superframe that represents: 12 amplitude samples of each of the 36 voice channels; one sample of each of the signals for the 36 channels; and also the alarm and framing signals. The binary pulses are applied to a binary-to-ternary converter which converts each sequence of four binary pulses to a group of three ternary pulses at a reduced pulse rate, so as to conserve the line bandwidth requirements. At the receiver, the ternary pulses are converted back to binary pulses for decoding and demultiplexing.

In the binary-ternary conversion, a conversion code is used which keeps the net positive and the net negative polarities of the ternary pulses on the line within selected limits so that the transformers in the equipment and on the line are subjected to as little direct current as possible. If the selected limits are exceeded,

this means that a faulty operation or conversion is taking place.

Accordingly, a primary object of our invention is to provide an error detector for detecting an excess of positive ternary pulses or anexcess of negative ternary pulses in a time-division multiplex, pulse-code modulation system.

Another object of our invention is to provide a new and improved circuit that receives positive and negative ternary pulses, and that produces an error signal either in response to the net number of positive pulses exceeding a selected limit or in response to the net number of negative pulses exceeding a selected limit.

SUMMARY OF THE INVENTION Briefly, these and other objects are achieved in accordance with our invention by a ternary code error detector which is preferably provided in the receiving portion at each end of a time-division multiplex, pulsecode modulation system. Or, our detector may be positioned at some location along the system, such asat an intermediate repeater. Our invention comprises a counter having two inputs, one of which receives the positive ternary pulses andone of which receives the negative ternary pulses. If the net count for either type pulse exceeds a selected limit, the counter input for that type pulse is blocked so that it can receive no more of that type of pulse. In addition, an error signal is produced. This error signal can be used to correct the condition, such as by switching to a different or standby system, or by switching to another transmission line between the transmitting and receiving portions, or by producing an alarm which calls for human intervention.

BRIEF DESCRIPTION OF THE DRAWING The subject matter which we regard as our invention is particularlypointedout anddistinctly claimed in the claims. The structure and operation of our invention, together with further objects and advantages, may be understood from the following description, given in connection with the accompanying drawing, in which:

FIG. 1 shows a general block diagram of a timedivision multiplex, pulse-code modulation transmitter and receiver for use in a TCS-27A or TCS-28 carrier system, and provided with a ternary code error detector in accordance with our invention;

FIG. 2 shows a table giving the makeup of the channels in each of the 12 frames forming a superframe in the system of FIG. 1;

FIG. 3 shows a table of the binary-ternary conversion 7 code used in the system of FIG. 1:;

FIG. 4 shows a logic circuit diagram of the ternary code error detector in accordance with our invention; and

FIG. 5 shows a table illustrating the operation of our error detector of FIG. 4.

DESCRIPTION OF THE PREFERRED EMBODIMENT In the following description, we will first give a general description of the TCS-27A or TCS-28 pulse-code modulation system with which our invention is intended to be used; and then give a detailed description of our ternary code error detector.

Pulse-Code Modulation Carrier System In the following description of the Carrier System, it has been assumed that the system is used with 36 voice channels. However, it is to be understood that almost any type of information can be transmitted by the 36 channels. Since a typical voice channel for telephone use has an upper frequency limit of something less than 4,000 Hertz, an amplitude-sampling rate of twice this, or 8,000 Hertz or pulses per second, has been selected in accordance with good engineering practice Such a sampling rate insures reasonably good fidelity and quality for ordinary telephone conversations. The Carrier System provides 36 voice channels, and one signaling, alarm, and framing channel. In order that each voice channel amplitude sample "655' b e adeqiiately represented, 128 different quantizing steps or amplitude levels are recognized. ln binary codes, these 128 different amplitude levels require seven digits or bits. The first bit is the most significant, and represents an amplitude level of 64. The second through the sixth bits respectively represent amplitude levels of 32, 16, 8, 4, and 2. The seventh bit is the least significant, and represents an amplitude level of l. The 37th channel for signaling,

alarm, and framing, comprises 5 bits. Under these specifications, 8,000 samples/channel-second, multiplied by seven bits/sample, multiplied by 36 channels (which totals 2,016,000 pulses or bits per second) plus 8,000 samples/channel-second, multiplied by five bits/sample. multiplied by 1 channel (which totals 40,000 pulses or bits per second) are required. This represents a total of 2.056 million pulses per second. Hence, the required basic clock or pulse-rate frequency is 2.056 million pulses per second.

As shown in H6. 1, the Carrier System has a timing circuit which supplies the basic clock or pulse frequency of 2.056 million pulses per second. In addition, the timing circuit 10 supplies other timed signals, including the following:

Signaling pulses SP1 through SP36 for operating the 36 signal gates 12 Channel pulses CP1 through CF36 for operating the odd and even channel voice gates 13, 14

Framing pulses FPl through FP12 for indicating each of the 12 frames of a superframe Channel bits CB1 through CB7 for indicating each of the seven bits which encode the voice channels or each of the five bits which encode the signaling,

alarm, and framing channel. Signaling, such as dialing or other information, is applied to the signal gates 12, and is gated through at an appropriate time by the signal pulses SP1 through SP36 to a combiner 18 for multiplexing. Since a relatively long time is required to encode each of the voice channels, two voice gates 13, 14, are used, these being respectively designated the odd-channel voice gates 13 and the e' en-channel voice gates 14. These gates 13, 14 repetitively sample the information (amplitude) of the voice channels in sequence (1, 3, 5, etc. and 2, 4, 6, etc., respectively), each channel being sampled 8,000 times per second. The odd channels 1 through 35 are gated by the odd channel pulses CPll through CF35 and the odd-channel voice gates 13 to an odd compress, sample, hold, and encoder circuit 15. In a similar manner, the even channels 2 through 36 are gated by the even channel pulses CP2 through CF36 and the even-channel voice gates 14 to an even compress, sample, hold, and encoder circuit 16. The signals applied to the circuits 15, 16 are time-division multiplex, amplitude-modulation pulses. In the circuits l5, 16, these pulses are compressed in accordance with conventional practice, to amplify or emphasize the lower signal amplitudes more than the higher signal amplitudes. However, it should be pointed out that such compression may be omitted. Each of the pulses is amplitude-sampled again, preferably at the end or during the last part of its respective first sample. Each of these second amplitude samples is held in a suitable time-delay circuit, and then encoded or quantized. That is, the amplitude of the held sample is measured or compared with respect to a reference level, and this measured level is then indicated by the 7 binary bits. For example, if the encoder recognizes 128 different amplitude levels (between 0 and 127), and if a held pulse has a measured level of 93 for example, this held pulse would be encoded as: l 0 l l l 1. In this code, the first (and most significant) bit is a l which represents 64. The second bit is a 0 which represents the absence of 32. The third bit is a 1 which represents 16. The fourth bit is a 1 which represents 8. The fifth bit is a 1 which represents 4. The sixth bit is a 0 which represents the absence of 2. And the seventh (and least significant) bit is a l which represents 1. The numbers e resergedbij 1 total 93:11. 2 99mins; 1 uti various timed signals from the timing circuit 10, combines these time-division multiplexed, encoded bits in the proper sequence beginning with Channel 1, and ending with Channel 36. After the Channel 36 coded pulses, five bits or pulses (representing signaling and alarm or framing) are then combined to provide a frame of 257 bits or pulses. This frame is repeated 8,000 times per second so that 257 multiplied by 8,000 or 2.056 million pulses per second are produced by the combiner 18. These pulses are then applied to a 4-to-3 converter 20 which converts the coded binary pulses having two levels (namely a 0 or 1) to coded ternary pulses having three levels (namely plus, zero, and minus). In this conversion, each successive group of four binary pulses is converted to three ternary pulses. Thus, the frequency of the ternary pulses is three-fourths the frequency of the binary pulses, or 1.542 million pulses per second. These ternary pulses are applied to the circuit or line, which typically comprises a pair of wires in a cable.

At the receiver, the ternary pulses (at a rate of 1.542 million pulses per second) are derived from a circuit or line and applied to timing circuits 22 which reproduce the basic pulse or clock frequency of 2.056 million pulses per second as well as other timing signals for use by various parts of the receiver. The incoming ternary pulses are also applied to an error detector 27 in accordance with our invention. The error detector 27 will be explained in detail below. The incoming ternary pulses are also applied to a 3-to-4 converter 23 which converts the ternary pulses back to corresponding binary pulses. ln this conversion, each successive group of three ternary pulses is converted to four binary pulses. This grouping is synchronized with or corresponds to the grouping used at the distant transmitter in order to provide proper decoding. These binary pulses, which have a rate of 2.056 million pulses per second, are applied to decoder and expand circuits 24 which convert successive groups of seven binary pulses back to audio signals corresponding to the audio signals at the transmitter, and which expand the converted signals to compensate for the compression that took place at the transmitter. The expanded audio signals are then applied to voice channel gates 26 which, with signals from the timing circuits 22, demultiplex the audio signals back to their respective voice channels 1 through 36. The binary pulses of Channel 37 are supplied by the converter 23 to signal gates 25 which, with signals from the timing circuits 22, provide signals for the respective voice channels 11 through 36. FIG. 1 shows the transmitter and receiver for only one terminal. Persons skilled in the art will appreciate that the transmitter of FIG. 1 would be used with a distant receiver, and that the receiver of FIG. 1 would be used with a distant transmitter. The distant transmitter and receiver would be respectively connected to the receiver and transmitter of FIG. 1 by two separate communication links, such as two pairs of wires.

FIG. 2 shows a table giving the makeup of the 37 channels in each of the 12 frames forming a superframe. In the top horizontal line, channels I through 37 are indicated. Since the makeup of the voice channels is the same, channels 3 through 35 are not shown separately, but are only indicated by a dashed line. In the next horizontal line, the seven digits or bits needed to encode the sampled amplitude are indicated. It will be noted that each of the voice or information channels 1 through 36 comprises seven such digits or bits. The 37th channel (for signaling, alarm, and framing) comprises only five digits or bits. In the third horizontal line, the frame bit numbers are indicated for the channels. It should be noted that each frame comprises 257 bits; bits 1 through 252 are for the 36 voice channels, and bits 253 through 257 are for the signaling, alarm, and framing channel 37. Below the third line in the lefthand column, the frame numbers I through 12 are indicated. In the vertical columns under the voice channels, the bits are marked by an X which indicates that the bits may be either a l or a in whatever combination is needed to encode amplitude levels 0 through 127. Channel 37 has a different makeup. Channel bit 3 of Channel 37 or frame bit 255 is marked by a Y for the first seven frames. This Y may be a 0 or 1 to indicate a particular condition for each of seven (or less) functions or operations in the system, such as in or out of frame, good or poor gain, and so forth. Channel bits 1, 2, 4, and 5 of Channel 37 (frame bits 253, 254, 256, 257) of the first nine frames respectively indicate the signaling information for the 36 channels as indicated by the designation 81 through S36. These bits are either a I to indicate a signal, or a 0 to indicate no signal. Generally, only one bit per channel per superframe is needed in order to provide the necessary signaling, since a superframe is repeated every 1.5 milliseconds. This is shown bythe following calculation:

257 pulses/frame X 12 frames/superframe/2,056,000 pulses/second 1.5 milliseconds/superframe In frames 10, 11, and 12, bits 1 through 5 of Channel 37 or frame bits 253 through 257 are used for system framing. These bits may have various logic sequences, but a preferred sequence is given in FIG. 2. The receiver is arranged with logic circuits so that if the selected framing logic sequence is not received in frames 10, 11, and 12 of Channel 37, the receiver causes its local transmitter to send an alarm. This alarm may be indicated by a 1 at one of the bits marked with a Y in FIG. 2. This 1 is sent to the distant terminal to cause the distant transmitter to send a distinguishing code of l 0 .0 0 0 0 0 continuously in all 36 voice channels. The

framing code used in Channel 37, frames 10, 11, and 12, is therefore readily distinguishable from the voice channels, so that synchronization, including proper grouping, can be quickly achieved. Provision of a separate Channel 37 for signaling, alarm, and framing is an important feature in that it permits the 36 voice channels to have only voice information, and hence provides a high quality system of 36 voice channels with a line rate of 1.542 million pulses per second.

FIG. 3 shows the binary-ternary conversion code which is used. This code is used in the 4-to-3 converter 20 of the transmitter to convert binary bits or pulses to ternary bits or pulses; and is used in the 3-to-4 converter 23 in the receiver to convert ternary pulses back to binary pulses. As explained earlier, the pulses supplied by the combiner 18 in the transmitter are a stream of binary pulses having a rate of 2.056 million pulses per second. These binary pulses are placed in groups of four pulses, and each group of four binary pulses is converted to a corresponding group of three ternary pulses so that the line frequency is reduced. At the receiver, the ternary pulses are placed in the same corresponding groups of three, and each group of three ternary pulses is converted back to binary pulses in the same corresponding groups of four. It is, of course, very important that the proper grouping be made so that correct decoding is provided. Otherwise, the information will be lost. In FIG. 3, the first vertical column shows binary groups of four pulses in all 16 possible combinations between four 0s and four ls. In the next two vertical columns, the corresponding ternary groups of three pulses are shown. These next two columns show a positive mode and a negative mode, since it is desirable that the net polarity weight (i.e., positive and negative), remain as near zero as possible. This is to insure that any transformers in the communication link have as little direct current as possible applied to them. The positive mode is used if the prior net polarity weight is negative, and the negative mode is used if the prior net polarity weight is zero or positive. For example, a binary group of four 0s is converted either to a ternary group of 0 0 in the positive mode, or 0 0 in the negative mode, depending upon what the net polarity weight was just prior to the appearance of that binary group of four 0s. If the prior net polarity weight was negative, then the positive ternary mode of 0 0 would be used. If the prior net polarity weight was zero or positive, then the negative ternary mode of 0 0 would be used. The last vertical column shows the net polarity weight provided by each of the ternary groups. Thus, for the binary group of four 0s, the ternary group has a polarity weight of 1 (either a plus or a minus, depending upon which mode is selected). At the receiver, the ternary groups are converted back to their corresponding binary groups as also indicated in FIG. 3. From FIG. 3, it will be seen that proper synchronization and grouping of the ternary pulses at the receiver are absolutely essential in order to get accurate (or any) information after decoding.

Ternary Error Code Detector An examination of FIG. 3 will show the maximum net positive and maximum net negative polarity weights which will be transmitted by the transmitter of FIG. 1.

The greatest polarity weight is 3, which occurs for the binary group 1 0 1. If the prior net polarity weight was negative, by the least amount, namely by -1, then the maximum change in the positive direction would be +3. Such a change would provide a net polarity weight of +2. However, if the prior net polarity weight was 0, then the maximum change in the negative direction would be 3. Such a change would result in a net polarity weight of 3. Thus, if the system is operating properly, the net polarity weight after a ternary group has been transmitted should never be more than +2 or less than -3. This provides or reduces the amount of direct current which line transformers are subjected to, and hence enhances their life. In accordance with our invention, this maximum limit or swing from +2 to 3 can also be used to indicate circuit conditions. Accordingly, we have provided a ternary code error detector which, for the code of FIG. 3, provides an error signal if the limits of +3 and 4 net are exceeded. We have provided an additional unit of polarity weight in each direction, namely'from +2 to +3 and from -3 to 4, in order to provide greater limits or tolerance. This is done because during transmission (as opposed to after transmission) of a ternary group, the +2 and 3 limits could be exceeded. For example, suppose the net count were +2, which calls for the negative mode, and this is followed by the binary group 0 0 l 0. The corresponding ternary group in the negative mode is 0. The first ternary pulse is which momentarily produces a net count of +3. In the negative mode, it is also possible for the net count to be -4 momentarily. However, it is to be understood that any limits may be set, dependingv upon the particular binary-ternary conversion code used and the amount of acceptable tolerance.

A logic circuit diagram of a preferred embodiment of our ternary code error detector 27 is shown in FIG. 4. Ternary pulses from the line are applied to the primary winding PW of an input transformer T1. The secondary winding SW of the transformer T1 is provided with a center tap which is connected to a point of ground or reference potential. The windings PW, SW of the transformer T1 are coupled together as indicated by the polarity dots. When an incoming ternary pulse is positive, the end 40 of the secondary winding SW is positive and the end 41 of the secondary winding is negative. When the incoming ternary pulse is negative, the end 40 of the secondary winding SW is negative, and the end 41 of the secondary winding SW is positive. The three wave forms shown around the transformer T1 illustrate this graphically. If a positive pulse is considered a logic 1, the end 40 produces a logic I only in response to positive ternary pulses and the end 41 produces a logic 1 only in response to negative ternary pulses.

Our circuit of FIG. 4 utilizes an up-down counter 42 which has two inputs, one designated a (or up) input and the other designated a (or down) input. The counter 42 has outputs designated 1, 2, and 4 which represent binary weights of l, 2 a n d 4 respectively. The counter 42 also has outputs l, 2, and 4 which are the logic inversions of the outputs 1, 2, and 4 respectively. Our circuit also utilizes a number of logic AND gates, such as the AND gate Gl-P. As known in the art, an AND gate requires that all of its inputs be at a logic 1 in order to produce a logic 1 at its output. If any input is at a logic 0, then the output of the AND gate is also a logic 0. We also utilize logic inverters, such as the inverter l-P. Such an inverter simply reverses the logic applied to its input. If a logic 1 is applied to an inverter, a logic 0 is produced. If a logic 0 is applied to an inverter, a logic 1 is produced. And finally, we utilize an OR gate, such as the error gate G-E. Such an OR gate produces a logic 1 at its output in response to any one of its inputs being at a logic 1. If all inputs to the OR gate are at a logic 0, then the output of the OR gate is a logic 0.

The l, 2, and 4 outputs of the counter 42 are applied to the three inputs of an AND gate 63-? and the I, 2, and 4 output of the counter 42 are applied to the three inputs of an AND gate G3-N. The output of the AND gate G3-P is applied to an AND gate Gl-P, and is applied through an inverter 1-? to an input of an AND gate G2-P. Similarly, the output of the AND gate G3-N is applied to an AND gate Gl-N, and is applied through an inverter l-N to aninput of an AND gate G2-N. The outputs of the AND gates G2-P,-G2-N are respectively applied to the input and input of the counter 42. The end 40 of the secondary winding SW is connected to the other input of the AND gate Gl-P and to the other input of the AND gate G2-P. Similarly, the end 41 of the secondary winding SW is connected to the other input of the AND gate G2-N and to the other input of the AND gate Gl-N. The outputs of the gates Gl-P,G1-N are applied to the two inputs of an OR gate G-E. This gate G-E produces an error signal which may be q lizsdiaths .SJLSEELQffIQ). ,1 292! way r The circuit of FIG. 4 is arranged so that if the counter 42 has a net count of three positive ternary pulses, an error signal will be produced if the next ternary pulse is positive. Likewise, if the counter 42 has a net count of four negative ternary pulses, the circuit of FIG. 4 will produce an error signal if the next ternary pulse is negative. The error signal for the excessive number of positive ternary pulses is produced at the output of the gate Gl-P, and the error signal for the excessive number of negative ternary pulses is produced at the output of the gate Gl-N. These error signals may be utilized individually, or may be applied to the OR gate G-E which produces an error signal in response to either of the individual error signals. A more detailed operation of our circuit of FIG. 4 can be understood by reference to the table of FIG. 5.

In FIG. 5, the left hand column shows an illustrative sequence of input ternary pulses. The remaining 13 columns show the conditions for various parts of the circuit of FIG. 4 following the application of each of the input ternary pulses. As a starting point, we have assumed that the counter 42 has a net count of zero. Hence, the 1, 2, and 4 outputs are at a logic 0, and the I, 2, and 4 outputs are at a logic 1. With the 1 and 2 outputs at a logic 0, the gate 63-? produces a logic 0. Likewise, with the 4 output at a logic0, the gate G3-N produces a logic 0. The logic 0 produced by the gate 03-? is inverted to apply a logic 1 to the gate G2-P so that the gate G2-P is open. The logic 0 produced by the gate G3-P closes the gate Gl-P. Similarly, the gate GZ-N is open and the gate Gl-N is closed. Next, we have assumed that a positive ternary pulse is applied. This causes the counter to have a net count of +1 and its outputs take the condition as shown. The gates G2-P, G2-N remain open, and the gates Gl-P and Gl-N remain closed. This condition is also present for the next positive pulse which gives a net count of +2. At the next positive pulse which gives a net count of +3, the output of the gate (33-? becomes a logic 1. This causes the gate GZ-P to close and the gate OH to open. However, the gate G2-N remains open and the gate Gl hl remains closed. The next pulse is also assumed to be a positive ternary pulse. However, since the gate (32% is closed, this pulse cannot reach the input so that counter condition remains the same, that is a count of +3. However, the gate Gl-P was previously open, so that it can produce a logic l in response to this fourth positive ternary pulse. This logic 1 is an error signal which can be used individually to indicate that the net positive polarity weight exceeds the limit, or which can be used in the gate G-E to provide an error signal to indicate that a polarity weight exceeds the limit. This condition is indicated by the asterisk for the gate Gl-P. Then, we have assumed that the next two pulses are negative so that the net count goes from +3 to +1. The condition shown for these lines prevail. Then, we have assumed another positive pulse which raises the count again to +2. Then, we have assumed two more negative input ternary pulses so that a net count of is present in the counter 42. At this time, the gates G2-P and G2-N are open, and the gates Gl-P and Gil-N are closed.

We have then assumed that the next ternary pulse is negative. This puts a net count of l in the counter 42, but an explanation of the counter condition is desirable at this point. Since the counter was previously at a 0, with its 1, 2, and 4 outputs at a logic 0, a count of 1 reverses the counter so that in effect it has a count of +7. Hence, the l, 2, and 4 outputs are at a logic 1. For the next 3 negative pulses, the conditions change as shown until the net count in the counter 42 is at a 4. At this point, it will be noted that the gate G2-N is closed and the gate Gl-N is open. The next negative pulse cannot reach the input, since the gate G2-N is closed. So the net count remains at 4. However, this pulse can pass through the gate Gl-N which was open. This is indicated by the asterisk in the column for Gl-N. Hence, an error signal is produced.

We have then assumed that four more positive ternary pulses are received, and this brings the circuit back to the condition originally assumed.

Conclusion It will thus be seen that we have provided a new and improved ternary code error detector for use in a timedivision multiplex, pulse-code modulation system. While we have shown only one embodiment, persons skilled in the art will appreciate that modifications may be made. For example, any limits for the positive (or up) count and any limits for the negative (or down) counts may be provided. Other types of positive and negative response circuits may be used. Similarly, other types of logic elements may be used. That is NAND and NOR gates may be substituted, and different types of counters may be substituted. In some cases, we have found that counters with a T, 2, and 1 output are not available. In such cases, the l, 2, and 4 outputs may be connected to inverters and connected to the gates (33-? and G3-N where appropriate. And finally, the OR gate G-E may be omitted and the error signals from the gates Gl-P, Gl-N may be used individually. Therefore, it is to be understood that modifications may be made toour invention. without departing from the spirit of the invention or from the scope of the claims.

What we claim as new and desire to secure by Letters Patent of the United States is:

1. For use in a time-division multiplex, pulse-code modulation system using a ternary code, an error detector for indicating that the net positive ternary pulse count exceeds a selected limit and for indicating that the net negative ternary pulse count exceeds a selected limit, said error detector comprising:

a. a first circuit adapted to be connected to said system for responding to positive ternary pulses;

b. a second circuit adapted to be connected to said system for responding to negative ternary pulses;

c. a counter havinga positive input, a negative input,

a plurality of normal outputs, and a plurality of inverted outputs;

d. a positive counter gate having a plurality of inputs respectively connected to selected ones of said counter outputs for producing a first signal in response to a selected positive count in said counter;

e. a negative counter gate having a plurality of inputs respectively connected to selected ones of said counter outputs for producing a second signal in response to a selected negative count in said counter;

a positive control gate connected between said first circuit and said positive input of said counter for applying positive ternary pulses thereto, said positive control gate being connected to the output of said positive counter gate for blocking said positive ternary pulses in response to said first signal;

g. a negative control gate connected between said second circuit and said negative input of said counter for applying negative ternary pulses thereto, said negative control gate being connected to the output of said negative counter gate for blocking said negative ternary pulses in response to said second signal;

h. a positive error gate connected to said first circuit, said positive error gate being connected to said positive counter gate for producing an error signal in response to said first signal and a subsequently received positive ternary pulse;

i. and a negative error gate connected to said second circuit, said negative error gate being connected to said negative counter gate for producing an error signal in response to said second signal and a subsequently received negative ternary pulse.

2. The error detector of claim 1 wherein said first signal is produced in response to a positive count of three in said counter, and said second signal is produced in response to a negative count of four in said counter.

3. An improved error detector for use in a system having ternary pulses therein comprising:

a. an input circuit adapted to be coupled to said system, said input circuit having a positive output for producing signals in response to positive ternary pulses and having a negative output for producing signals in response to negative ternary pulses;

b. an up-down counter having a positive input, a negative input, and having 1, I, 2, 2, 4, and I outputs;

c. a first positive AND gate having at least three inputs respectively connected to l, 2, and Z outputs of said counter;

a first negative AND gate having at least three inputs respectively connected to said I, i, and 4 outputs of said counter;

a second positive AND gate having at least two inputs, one of said second positive AND gate inputs being connected to said positive output and the other of said second positive AND gate inputs being connected through an inverter to the output of said first positive AND gate;

a second negative AND gate having at least two inputs, one of said second negative AND gate inputs being connected to said negative output and the other of said second negative AND gate inputs being connected through an inverter to the output 12 of said first negative AND gate;

g. a positive error AND gate having at least two inh. and a negative error AND gate having at least two inputs, one of said negative error AND gate inputs being connected to said negative output and the other of said negative error AND gate inputs being connected to said output of said first negative AND UNITEn STATES PATENT OFFICE CERTIFICATE OF CORRQTION Patent No. 3,842,401 Dated October 15, 1.974

Inventor) James S. Smith, Jr. James W. Williams It is certified that error appears in the above-identified patent and that said Letters Patent are hereby corrected as shown below:

Col. 3, line 57 I cancel "e'en" and insert even Col. 8, line 28 cancel "FIG)" and insert FIG Signed and sealed this 11th day of March 1.975.

(SEAL) Attest:

- C. MARSHALL DANN RUTH C. MASON Commissioner of Patents Attesti-ng Officer and Trademarks 

1. For use in a time-division multiplex, pulse-code modulation system using a ternary code, an error detector for indicating that the net positive ternary pulse count exceeds a selected limit and for indicating that the net negative ternary pulse count exceeds a selected limit, said error detector comprising: a. a first circuit adapted to be connected to said system for responding to positive ternary pulses; b. a second circuit adapted to be connected to said system for responding to negative ternary pulses; c. a counter having a positive input, a negative input, a plurality of normal outputs, and a plurality of inverted outputs; d. a positive counter gate having a plurality of inputs respectively connected to selected ones of said counter outputs for producing a first signal in response to a selected positive count in said counter; e. a negative counter gate having a plurality of inputs respectively connected to selected ones of said counter outputs for producing a second signal in response to a selected negative count in said counter; f. a positive control gate connected between said first circuit and said positive input of said counter for applying positive ternary pulses thereto, said positive control gate being connected to the output of said positive counter gate for blocking said positive ternary pulses in response to said first signal; g. a negative control gate connected between said second circuit and said negative input of said counter for applying negative ternary pulses thereto, said negative control gate being connected to the output of said negative counter gate for blocking said negative ternary pulses in response to said second signal; h. a positive error gate connected to said first circuit, said positive error gate being connected to said positive counter gate for producing an error signal in response to said first signal and a subsequently received positive ternary pulse; i. and a negative error gate connected to said second circuit, said negative error gate being connected to said negative counter gate for producing an error signal in response to said second signal and a subsequently received negative ternary pulse.
 2. The error detector of claim 1 wherein said first signal is produced in response to a positive count of three in said counter, and said second signal is produced in response to a negative count of four in said counter.
 3. An improved error detector for use in a system having ternary pulses therein comprising: a. an input circuit adapted to be coupled to said system, said input circuit having a positive output for producing signals in response to positive ternary pulses and having a negative output for producing signals in response to negative ternary pulses; b. an up-down counter having a positive input, a negative input, and having 1, 1, 2, 2, 4, and 4 outputs; c. a first positive AND gate having at least three inputs respectively connected to 1, 2, and 4 outputs of said counter; d. a first negative AND gate having at least three inputs respectively connected to said 1, 2, and 4 outputs of said counter; e. a second positive AND gate having at least two inputs, one of said second positive AND gate inputs being connected to said positive output and the other of said second positive AND gate inputs being connected through an inverter to the output of said first positive AND gate; f. a second negative AND gate having at least two inputs, one of said second negative AND gate inputs being connected to said negative output and the other of said second negative AND gate inputs being connected through an inverter to the output of said first negative AND gate; g. a positive error AND gate having at least two inputs, one of said positive error AND gate inputs being connected to said positive output and the other of said positive error AND gate inputs being connected to said output of said first positive AND gate; h. and a negative error AND gate having at least two inputs, one of said negative error AND gate inputs being connected to said negative output and the other of said negative error AND gate inputs being connected to said output of said first negative AND gate. 